EPC16UC88 vs EPC16UC8B Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC16UC88 sa pamamagitan ng Altera at EPC16UC8B sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC16UC88 | EPC16UC8B |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | FPGA & CPLD |
| Katayuan ng Lifecycle | Unknown | NRND |
| Device Type | In-system programmable configuration PROM for FPGAs | — |
| Configuration Memory Capacity | 16 Mb | — |
| Volte ng Pagbibigay | 3.3 V core and I/O | — |
| Packhaging | 88-UBGA (11x8) | 8-pin QFP (UC8B suffix) |
| Package Family | UBGA | — |
| In-System Programmability | IEEE Std. 1532 compatible | — |
| Programming Language Support | Jam Standard Test and Programming Language (STAPL) | — |
| JTAG Boundary Scan | Supported | — |
| nINIT_CONF Function | Allows private JTAG instruction to start FPGA configuration | — |
| Configuration Architecture | Configuration controller and flash memory | — |
| FPGA Configuration Use | Automatic configuration after power-up or system initialization | — |
| Data Output | Configuration data output controlled by OE and nCS | — |
| Output Control | OE and nCS control tri-state buffer and address counter | — |
| Uri ng Pagpapasok | Surface mount | Surface Mount |
| Package Dimensions | 11 mm x 8 mm | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature] | [DATA_NEEDED: Operating temperature range] |
| Output Current | [DATA_NEEDED: output current] | — |
| Configuration Frequency | [DATA_NEEDED: configuration frequency] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Product Type | — | Enhanced Configuration Device |
| Manufacturer | — | Intel (formerly Altera) |
| Configuration Memory Density | — | 16 Mb |
| FPGA Family Supported | — | Altera SRAM-based LUT FPGAs (Cyclone, Stratix, APEX) |
| Configuration Modes | — | Passive Serial (PS), Passive Parallel Asynchronous (PPA), Passive Parallel Synchronous (PPS), Fast Passive Parallel (FPP) |
| Core Supply Voltage (VCC) | — | 3.3 V |
| I/O Supply Voltage (VIO) | — | 1.8 V / 2.5 V / 3.3 V |
| Programmability | — | In-system programmable via IEEE 1532 / JTAG |
| Configuration Pages | — | 16 pages x 1 Mb each |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Lead-Free | — | [DATA_NEEDED: Lead-free status] |
| Handshake Pins | — | nSTATUS, CONF_DONE, nCONFIG, OE |
| Family | — | EPC16 (Enhanced Configuration) |