EPC20LC20U vs EPC21LC20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC20LC20U sa pamamagitan ng Intel at EPC21LC20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPC21LC20 - Altera 2 Mb Config PROM for SRAM-based LUT Devices | PLCC-20
EPC21LC20 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPC20LC20U | EPC21LC20 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Manufacturer | Altera Corporation (now Intel) | — |
| Fungsi | FPGA Configuration Device (Serial Configuration PROM) | — |
| Uri ng Memory | Non-volatile configuration memory | Serial Configuration PROM (Flash-based, in-system programmable) |
| Configuration Interface | Serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, OE) | — |
| Operating Voltage | 5.0 V (typical) | — |
| Absolute Maximum DC Input | -0.3 V to 7.0 V | — |
| Transient Input Tolerance | -2.0 V undershoot to 7.0 V overshoot (<100 mA, <20 ns) | — |
| Package Type | PLCC-20 (J-lead, plastic leaded chip carrier) | — |
| Bilang ng Pin | 20 | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket or solder) |
| Compatible FPGA Families | Altera FLEX 6000, FLEX 8000, FLEX 10K, APEX, ACEX, early Cyclone | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) |
| In-System Programming | Supported via JTAG / Quartus programmer | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: confirm from Altera product page] |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: industrial/commercial grade] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Katayuan ng Lifecycle | Obsolete / Last-time-buy in distribution | — |
| Density | — | 2 Mb (2,097,152 bits) |
| Configuration Mode Supported | — | Serial (PS) for Altera SRAM-based LUT FPGAs |
| Maximum DCLK Frequency | — | 10 MHz |
| Access Time | — | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] |
| Programming Interface | — | IEEE 1149.1 (JTAG) |
| Program/Erase Endurance | — | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] |
| Operating Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| Standby Current | — | [DATA_NEEDED: ICCSB value] |
| Active Read Current | — | [DATA_NEEDED: ICC active current] |
| Operating Temperature (commercial) | — | 0 °C to +70 °C (LC suffix) |
| Operating Temperature (industrial) | — | [DATA_NEEDED: -40 to +85 °C for LI variant] |
| Packhaging / Kaso | — | 20-pin PLCC (J-lead, JEDEC MS-018) |
| Level ng MSL | — | [DATA_NEEDED: confirm moisture sensitivity level] |
| Lead-Free (Pb-free) | — | [DATA_NEEDED: confirm] |
| JTAG Boundary-Scan Compliant | — | Yes (IEEE Std 1149.1) |
| Data Width | — | 1 bit (serial DATA output) |