EPC20LC20U vs EPC21LC20 比較

詳細並排比較 EPC20LC20U 由 Intel 與 EPC21LC20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC20LC20U EPC21LC20
品牌 Intel Intel
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete 啟用中
Manufacturer Altera Corporation (now Intel) —
功能 FPGA Configuration Device (Serial Configuration PROM) —
記憶體類型 Non-volatile configuration memory Serial Configuration PROM (Flash-based, in-system programmable)
Configuration Interface Serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, OE) —
Operating Voltage 5.0 V (typical) —
Absolute Maximum DC Input -0.3 V to 7.0 V —
Transient Input Tolerance -2.0 V undershoot to 7.0 V overshoot (<100 mA, <20 ns) —
Package Type PLCC-20 (J-lead, plastic leaded chip carrier) —
腳位數 20 —
安裝類型 Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket or solder)
Compatible FPGA Families Altera FLEX 6000, FLEX 8000, FLEX 10K, APEX, ACEX, early Cyclone ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT)
In-System Programming Supported via JTAG / Quartus programmer —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: confirm from Altera product page]
工作溫度範圍 [DATA_NEEDED: industrial/commercial grade] —
Lead-Free / Halogen-Free [DATA_NEEDED: lead-free status] —
生命週期狀態 Obsolete / Last-time-buy in distribution —
Density — 2 Mb (2,097,152 bits)
Configuration Mode Supported — Serial (PS) for Altera SRAM-based LUT FPGAs
Maximum DCLK Frequency — 10 MHz
Access Time — approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure]
Programming Interface — IEEE 1149.1 (JTAG)
Program/Erase Endurance — 100 cycles minimum [DATA_NEEDED: confirm from datasheet]
Operating Voltage (VCC) — 3.0 V to 3.6 V (3.3 V typical)
Standby Current — [DATA_NEEDED: ICCSB value]
Active Read Current — [DATA_NEEDED: ICC active current]
Operating Temperature (commercial) — 0 °C to +70 °C (LC suffix)
Operating Temperature (industrial) — [DATA_NEEDED: -40 to +85 °C for LI variant]
封裝 / 外殼 — 20-pin PLCC (J-lead, JEDEC MS-018)
MSL 等級 — [DATA_NEEDED: confirm moisture sensitivity level]
Lead-Free (Pb-free) — [DATA_NEEDED: confirm]
JTAG Boundary-Scan Compliant — Yes (IEEE Std 1149.1)
Data Width — 1 bit (serial DATA output)

資料表與資源

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