EPC2TC32-U-CAF48 vs EPC2T32U-CAF48 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2TC32-U-CAF48 sa pamamagitan ng Altera at EPC2T32U-CAF48 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPC2T32U-CAF48 - Altera/Intel 2Mb Config Device, 8MHz, 48-QFN | XAIPART
EPC2T32U-CAF48 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPC2TC32-U-CAF48 | EPC2T32U-CAF48 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | Memory ICs |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Laki ng Memory | 1.6 Mb | — |
| Fungsi | In-system programmable configuration PROM | — |
| Volte ng Pagbibigay | 3.3 V | — |
| Interface | Serial synchronous (Altera FPGA configuration) | — |
| Programming Interface | IEEE 1149.1 JTAG | IEEE 1149.1 (JTAG) / IEEE 1532 |
| Control Pins | OE, nCS, DCLK | — |
| Cascadable | Yes (DATA output supports daisy-chain) | — |
| Storage Technology | EPROM | — |
| Packhaging | 32-TQFP (7x7 mm) | 48-pin QFN (CAF suffix) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40C to +85C (industrial, per data sheet) | -40 C to +85 C (industrial grade, "U") |
| Bilang ng Pin | 32 | — |
| DC Input Min | -0.3 V | — |
| DC Input Overshoot | 7.0 V for <100 mA, <20 ns | — |
| DC Input Undershoot | -2.0 V for <100 mA, <20 ns | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Uri ng Memory | — | Non-volatile flash configuration memory |
| Memory Density | — | 2 Mb (2097152 bits) |
| Configuration Interface | — | Altera FPP (8-bit) / PS (4-wire) / AS (serial) |
| Maximum Configuration Clock (DCLK) | — | 8 MHz |
| Supply Voltage (VCC) | — | 3.3 V (typical) |
| I/O Tolerance | — | 5 V tolerant |
| Program/Erase Endurance | — | 10,000 cycles per sector minimum |
| Data Retention | — | 20 years minimum |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Lead-Free Finish | — | Yes (CAF suffix indicates lead-free) |
| Supported FPGA Families | — | Cyclone, Cyclone II, Stratix, APEX 20K, ACEX 1K, Mercury, Excalibur |