EPC2TI32N vs EPC2-TI32 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2TI32N sa pamamagitan ng Altera at EPC2-TI32 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2TI32N | EPC2-TI32 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Uri ng Memory | In-System Programmable Configuration PROM (Flash) | In-System Programmable Configuration PROM |
| Laki ng Memory | 1.6 Mbit | 1.6 Mbit |
| Programmable Type | In System Programmable (ISP via JTAG) | — |
| Uri ng Interface | Parallel configuration data output + JTAG (IEEE 1149.1) ISP | — |
| Supply Voltage - 3.3V Mode | 3.0 V to 3.6 V | — |
| Supply Voltage - 5V Mode | 4.5 V to 5.5 V | — |
| Temperature na Operasyon | -40C to +85C | [DATA_NEEDED: Operating temperature range] |
| Packhaging / Kaso | 32-TQFP (7x7 mm) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, Mercury, FLEX 10K | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II |
| JTAG Interface | Yes (IEEE 1149.1 compliant TAP for ISP) | — |
| Configuration Pins | nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA[7:0] | nCONFIG, nSTATUS, CONF_DONE (open-drain) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Free | [DATA_NEEDED: lead-free status] | — |
| Interface | — | Serial configuration, 10 MHz |
| Volte ng Pagbibigay | — | 3.3 V |
| I/O Tolerance | — | 5 V tolerant |
| Packhaging | — | 32-pin TQFP (7x7 mm) |
| Programming Interface | — | JTAG (IEEE 1149.1) |
| Multi-Device Daisy-Chain Support | — | Yes |
| Lead-Free | — | [DATA_NEEDED: Lead-free status] |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |