EPC2TI32N vs EPC2TC32N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2TI32N sa pamamagitan ng Altera at EPC2TC32N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2TI32N | EPC2TC32N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Uri ng Memory | In-System Programmable Configuration PROM (Flash) | Flash Configuration PROM |
| Laki ng Memory | 1.6 Mbit | 1.6 Mbit |
| Programmable Type | In System Programmable (ISP via JTAG) | In System Programmable (ISP) |
| Uri ng Interface | Parallel configuration data output + JTAG (IEEE 1149.1) ISP | — |
| Supply Voltage - 3.3V Mode | 3.0 V to 3.6 V | — |
| Supply Voltage - 5V Mode | 4.5 V to 5.5 V | — |
| Temperature na Operasyon | -40C to +85C | 0 °C to +70 °C (Commercial) |
| Packhaging / Kaso | 32-TQFP (7x7 mm) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, Mercury, FLEX 10K | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| JTAG Interface | Yes (IEEE 1149.1 compliant TAP for ISP) | — |
| Configuration Pins | nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA[7:0] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | — | Altera (now Intel) |
| Interface | — | JTAG (IEEE 1149.1) + serial/parallel |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Supply Voltage - VCCIO | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Max Configuration Clock | — | 8 MHz |
| Packhaging | — | 32-TQFP (7x7 mm) |
| Daisy-Chain Support | — | Yes (multi-FPGA cascade) |
| JTAG Compliance | — | IEEE 1149.1 |
| Configuration Mode | — | Serial (AS) or Parallel (PS/AP) |