EPC2TI32N vs EPC2TC32N 比較
詳細並排比較 EPC2TI32N 由 Altera 與 EPC2TC32N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2TI32N | EPC2TC32N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | Obsolete |
| 記憶體類型 | In-System Programmable Configuration PROM (Flash) | Flash Configuration PROM |
| 記憶體容量 | 1.6 Mbit | 1.6 Mbit |
| Programmable Type | In System Programmable (ISP via JTAG) | In System Programmable (ISP) |
| 介面類型 | Parallel configuration data output + JTAG (IEEE 1149.1) ISP | — |
| Supply Voltage - 3.3V Mode | 3.0 V to 3.6 V | — |
| Supply Voltage - 5V Mode | 4.5 V to 5.5 V | — |
| 工作溫度 | -40C to +85C | 0 °C to +70 °C (Commercial) |
| 封裝 / 外殼 | 32-TQFP (7x7 mm) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, Mercury, FLEX 10K | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| JTAG Interface | Yes (IEEE 1149.1 compliant TAP for ISP) | — |
| Configuration Pins | nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA[7:0] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | — | Altera (now Intel) |
| 介面 | — | JTAG (IEEE 1149.1) + serial/parallel |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Supply Voltage - VCCIO | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Max Configuration Clock | — | 8 MHz |
| 封裝 | — | 32-TQFP (7x7 mm) |
| Daisy-Chain Support | — | Yes (multi-FPGA cascade) |
| JTAG Compliance | — | IEEE 1149.1 |
| Configuration Mode | — | Serial (AS) or Parallel (PS/AP) |