EPC4QI100N vs EPC4Q100N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC4QI100N sa pamamagitan ng Altera at EPC4Q100N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPC4QI100N - 4Mb In-System Programmable FPGA Config PROM | Altera (Intel)
EPC4QI100N ✓ Nakahanda
Pagsanggunian na paghahambing
| Parametro | EPC4QI100N | EPC4Q100N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Presyo ng Yunit (USD) | $10.40 | — |
| Uri ng Memory | In-System Programmable Configuration PROM (NOR flash) | Flash (NOR, Enhanced Configuration Device) |
| Laki ng Memory | 4 Mbit (4,194,304 bits) | 4 Mbit (512 Kbyte) |
| Programmable Type | In System Programmable (ISP via JTAG) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Interface | Altera serial (x1) configuration + JTAG | — |
| Configuration Clock DCLK | [DATA_NEEDED: DCLK maximum frequency] | — |
| Active Supply Current (ICC active) | [DATA_NEEDED: ICC active typical value] | — |
| Standby Supply Current | [DATA_NEEDED: ICC standby typical value] | — |
| Temperature na Operasyon | -40C to +85C (industrial) | -40 C to +85 C (industrial) |
| Storage Temperature | -65C to +150C | — |
| Packhaging | 100-pin PQFP (PowerPQFP, 20x14 mm) | 100-pin PQFP |
| Package Code | QI100 (PQFP-100, industrial) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: per JEDEC J-STD-020] |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | — |
| JTAG Standard | IEEE 1149.1 boundary-scan / ISP | — |
| Cascading | Supported (multi-device daisy chain) | — |
| Target FPGAs | Altera Cyclone, Cyclone II, Stratix series | — |
| Configuration Interface | — | Serial (FLEX) / Parallel / JTAG ISP |
| Volte ng Pagbibigay | — | 3.3 V |
| Program/Erase Cycles | — | [DATA_NEEDED: minimum endurance in cycles] |
| JTAG Support | — | IEEE 1149.1 compliant |
| In-System Programmable | — | Yes |
| Target FPGA Families | — | Cyclone, Stratix, APEX, Mercury, ACEX |
| Data Width (parallel mode) | — | 8-bit |
| Lead-Free / RoHS | — | [DATA_NEEDED: per lot] |
| Status | — | Not Recommended for New Designs (NRND) |
| Configuration Schemes | — | Active Serial (AS) / Active Parallel (AP) / Passive Serial (PS) |