EPF10K100EFC484-3 vs EPF10K50EFC484-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K100EFC484-3 sa pamamagitan ng Altera at EPF10K50EFC484-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPF10K50EFC484-2 - 50K Gates FLEX-10KE FPGA, 484-BGA | Intel / Altera
EPF10K50EFC484-2 ObsoletePagsanggunian na paghahambing
| Parametro | EPF10K100EFC484-3 | EPF10K50EFC484-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | FLEX 10KE | FLEX-10KE |
| Typical Gates | 100,000 | 50,000 |
| Maximum System Gates | 158,000 | — |
| Logic Elements | 4,992 | — |
| Logic Array Blocks (LABs) | 624 | — |
| Embedded Memory (EAB RAM) | 49,152 bits | — |
| User I/O Pins | 338 | — |
| Speed Grade | -3 (fastest commercial) | -2 |
| Packhaging | 484-ball FineLine BGA | 484-ball FineLine BGA (FBGA) |
| Temperature na Operasyon | 0C to +70C (Commercial) | 0 C to +70 C (Commercial) |
| Core Voltage | 2.5 V | 2.5 V |
| I/O Standards Supported | 2.5V / 3.3V / 5.0V (PCI-compliant) | — |
| JTAG Support | IEEE Std. 1149.1-1990 BST | — |
| Configuration Method | SRAM (volatile, requires configuration device) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements (LEs) | — | 2,880 |
| Embedded Memory (Bits) | — | 40,960 |
| Embedded Array Blocks (EABs) | — | 12 (each 2,048 bits) |
| Maximum User I/O Pins | — | 220 |
| Process Technology | — | 0.22 micrometer CMOS |
| Internal Frequency | — | 200 MHz |
| JTAG Boundary-Scan | — | IEEE Std. 1149.1-1990 compliant |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 at 33/66 MHz (3.3 V); 5.0 V at speed grade -1 |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |