EPF10K130EBC356-3 vs EPF10K130EBC356-1N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K130EBC356-3 sa pamamagitan ng Altera at EPF10K130EBC356-1N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPF10K130EBC356-3 EPF10K130EBC356-1N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family FLEX-10KE FLEX 10KE
Series FLEX-10KE —
Typical Gates 130,000 130,000
Logic Elements 8,192 —
Logic Array Blocks (LABs) 832 —
Embedded Array Blocks (EABs) 12 [DATA_NEEDED: EAB count for EPF10K130E]
Total RAM Bits 24,576 bits (12 EABs × 2 Kbit) 65,536
Maximum User I/Os 274 —
Core Supply Voltage 2.375 V to 2.625 V 2.5 V
I/O Supply Voltage 2.5 V / 3.3 V / 5.0 V (multiVolt I/O) 3.3 V
Pin-to-Pin Propagation Delay (-3 grade) 0.6 ns —
Temperature na Operasyon 0 °C to +70 °C (Commercial) 0 °C to 70 °C (Commercial)
Packhaging 356-LBGA (35x35 mm) 356-LBGA
Uri ng Pagpapasok Surface Mount Surface Mount
Logic Family CMOS CMOS
Process Technology 0.22 µm SRAM-based CMOS 0.22 µm
Configuration Method SRAM-based, JTAG (IEEE 1149.1) in-system programmable —
Speed Grade -3 (fastest) -1
Tindminan RoHS Non-compliant (SnPb ball finish on legacy BGA) [DATA_NEEDED: RoHS compliance for EPF10K130EBC356-1N]
Lead-Free No —
Lifecycle Obsolete — last-time-buy / Rochester Electronics stock only —
Maximum System Gates — [DATA_NEEDED: maximum system gates for EPF10K130E]
Logic Elements (LEs) — 6,656
User I/O Pins — 274
Package Code — LBGA
Propagation Delay — 0.6 ns
Maximum Internal Frequency — 333.33 MHz
JTAG Boundary-Scan — IEEE Std. 1149.1-1990 compliant
PCI Compliance — PCI Local Bus Specification Rev. 2.2 (33/66 MHz, 3.3 V and 5.0 V)

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita