EPF10K200EBI600-2N vs EPF10K130EFC672-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K200EBI600-2N sa pamamagitan ng Intel at EPF10K130EFC672-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPF10K200EBI600-2N | EPF10K130EFC672-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | FLEX 10KE | FLEX 10KE |
| Typical Gates | 200,000 | — |
| Maximum System Gates | 513,000 | — |
| Logic Elements (LEs) | 9,984 | — |
| Embedded Array Blocks (EABs) | 12 | — |
| Total RAM Bits | 98,304 | — |
| User I/O Pins | 470 | — |
| Dedicated Inputs | 6 | — |
| Packhaging | 600-ball BGA (45 mm x 45 mm, 1.27 mm pitch) | 672-ball FineLine BGA |
| Technology / Process | 0.22 µm CMOS SRAM | — |
| Core Supply Voltage | 2.5 V (2.3 V to 2.7 V) | 2.5 V |
| I/O Supply Voltage | 2.5 V / 3.3 V (5 V tolerant I/O available) | — |
| Propagation Delay | 0.4 ns to 0.6 ns (per LE) | — |
| Maximum Internal Frequency | 200 MHz | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (Commercial) |
| Configuration Method | SRAM, JTAG (IEEE 1149.1), serial configuration EPROM | — |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Logic Elements / Cells | — | 6,656 |
| Total Gates | — | ~130,000 |
| Logic Array Blocks (LABs) | — | 832 |
| Embedded Memory (RAM bits) | — | 65,536 |
| Maximum User I/Os | — | 413 |
| Number of I/O Pins | — | 672 (package pins) |
| Process Technology | — | 0.22 µm CMOS |
| Propagation Delay (typ.) | — | 0.6 ns |
| Internal Operating Frequency (max) | — | 333.33 MHz |
| Speed Grade | — | -2 |
| Programming Method | — | SRAM-based, JTAG (IEEE 1149.1) |