EPF10K200EFC672-3 vs EPF10K200SFC672-1X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K200EFC672-3 sa pamamagitan ng Intel at EPF10K200SFC672-1X sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPF10K200EFC672-3 - FLEX 10KE FPGA 9984 Cells 470 I/O BGA-672 | Intel
EPF10K200EFC672-3 Obsolete
Pagsanggunian na paghahambing
| Parametro | EPF10K200EFC672-3 | EPF10K200SFC672-1X |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | FLEX 10KE | FLEX-10KS |
| Number of Logic Elements / Cells | 9,984 | — |
| Number of LABs / CLBs | 1248 | — |
| Total RAM Bits | 98,304 bits (12 EABs of 8 Kbits) | — |
| Number of I/O | 470 | — |
| Number of Gates (typical) | 200,000 | — |
| Supply Voltage - Operating | 2.3 V to 2.7 V (2.5 V nominal) | — |
| Process Technology | 0.22 µm CMOS | — |
| Maximum Operating Frequency | 166.67 MHz | — |
| Propagation Delay | 0.4 ns | 0.4 ns |
| Packhaging / Kaso | 672-BBGA (27 x 27 mm, 1.0 mm pitch, FineLine BGA) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | 0 °C to 70 °C (Commercial) |
| Configuration Memory | SRAM-based (volatile, requires external configuration device) | — |
| Number of PLLs | 4 | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance status] |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | FLEX 10K (legacy) |
| Architecture | — | Reconfigurable CMOS SRAM |
| Typical System Gates | — | 200,000 |
| Maximum System Gates | — | [DATA_NEEDED: maximum system gate count] |
| Logic Elements (LEs) | — | 9,984 |
| Logic Array Blocks (LABs) | — | 1,248 |
| Embedded Array Blocks (EABs) | — | 24 |
| Embedded RAM Bits | — | 98,304 |
| User I/O Pins | — | 470 |
| Core Supply Voltage | — | 2.375 V to 2.625 V (2.5 V nominal) |
| JTAG Support | — | IEEE Std. 1149.1 (adds up to 31,250 gates) |
| Packhaging | — | 672-ball FineLine BGA, 27 × 27 mm, 1.0 mm pitch |
| Logic Family | — | CMOS |
| Configuration Method | — | SRAM (volatile, reconfigurable at every power-up) |
| Design Tool | — | Quartus (legacy FLEX 10K support) |