EPF10K200SFC672-1X vs EPF10K200SFC672-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K200SFC672-1X sa pamamagitan ng Intel at EPF10K200SFC672-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPF10K200SFC672-1X | EPF10K200SFC672-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | FLEX-10KS | FLEX 10KE |
| Family | FLEX 10K (legacy) | — |
| Architecture | Reconfigurable CMOS SRAM | — |
| Typical System Gates | 200,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gate count] | — |
| Logic Elements (LEs) | 9,984 | — |
| Logic Array Blocks (LABs) | 1,248 | 1,248 |
| Embedded Array Blocks (EABs) | 24 | — |
| Embedded RAM Bits | 98,304 | — |
| User I/O Pins | 470 | 470 |
| Propagation Delay | 0.4 ns | — |
| Core Supply Voltage | 2.375 V to 2.625 V (2.5 V nominal) | 2.5 V (2.375 V to 2.625 V) |
| JTAG Support | IEEE Std. 1149.1 (adds up to 31,250 gates) | — |
| Temperature na Operasyon | 0 °C to 70 °C (Commercial) | 0 °C to +70 °C (Commercial) |
| Packhaging | 672-ball FineLine BGA, 27 × 27 mm, 1.0 mm pitch | 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch |
| Uri ng Pagpapasok | Surface Mount | — |
| Logic Family | CMOS | — |
| Configuration Method | SRAM (volatile, reconfigurable at every power-up) | SRAM-based, passive parallel asynchronous |
| Design Tool | Quartus (legacy FLEX 10K support) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements | — | 9,984 |
| System Gates | — | 200,000 |
| Embedded Memory (bits) | — | 98,304 |
| Process Technology | — | 0.22 µm CMOS |
| I/O Supply Voltage | — | MultiVolt 2.5 V / 3.3 V / 5.0 V |
| Speed Grade | — | -2 |
| Internal Propagation Delay | — | 0.4 ns |
| Maximum Operating Frequency | — | 200 MHz |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| On-chip PLL | — | Yes |