EPF10K200SFC672-1X vs EPF10K200SFC672-2 比較

詳細並排比較 EPF10K200SFC672-1X 由 Intel 與 EPF10K200SFC672-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPF10K200SFC672-1X EPF10K200SFC672-2
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Series FLEX-10KS FLEX 10KE
Family FLEX 10K (legacy) —
Architecture Reconfigurable CMOS SRAM —
Typical System Gates 200,000 —
Maximum System Gates [DATA_NEEDED: maximum system gate count] —
Logic Elements (LEs) 9,984 —
Logic Array Blocks (LABs) 1,248 1,248
Embedded Array Blocks (EABs) 24 —
Embedded RAM Bits 98,304 —
User I/O Pins 470 470
Propagation Delay 0.4 ns —
Core Supply Voltage 2.375 V to 2.625 V (2.5 V nominal) 2.5 V (2.375 V to 2.625 V)
JTAG Support IEEE Std. 1149.1 (adds up to 31,250 gates) —
工作溫度 0 °C to 70 °C (Commercial) 0 °C to +70 °C (Commercial)
封裝 672-ball FineLine BGA, 27 × 27 mm, 1.0 mm pitch 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch
安裝類型 Surface Mount —
Logic Family CMOS —
Configuration Method SRAM (volatile, reconfigurable at every power-up) SRAM-based, passive parallel asynchronous
Design Tool Quartus (legacy FLEX 10K support) —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Logic Elements — 9,984
System Gates — 200,000
Embedded Memory (bits) — 98,304
Process Technology — 0.22 µm CMOS
I/O Supply Voltage — MultiVolt 2.5 V / 3.3 V / 5.0 V
Speed Grade — -2
Internal Propagation Delay — 0.4 ns
Maximum Operating Frequency — 200 MHz
Boundary Scan — IEEE 1149.1 (JTAG)
On-chip PLL — Yes

資料表與資源

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