EPF10K200SFC672-2 vs EPF10K200EFC672-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K200SFC672-2 sa pamamagitan ng Altera at EPF10K200EFC672-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPF10K200SFC672-2 | EPF10K200EFC672-2 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Series | FLEX 10KE | — |
| Logic Elements | 9,984 | 9,984 |
| System Gates | 200,000 | — |
| Logic Array Blocks (LABs) | 1,248 | 624 |
| User I/O Pins | 470 | — |
| Embedded Memory (bits) | 98,304 | — |
| Process Technology | 0.22 µm CMOS | 0.22 um CMOS |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | — |
| I/O Supply Voltage | MultiVolt 2.5 V / 3.3 V / 5.0 V | — |
| Speed Grade | -2 | -2 |
| Internal Propagation Delay | 0.4 ns | — |
| Maximum Operating Frequency | 200 MHz | — |
| Packhaging | 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch | 672-BBGA (FineLine BGA) |
| Temperature na Operasyon | 0 °C to +70 °C (Commercial) | 0 C to 70 C |
| Configuration Method | SRAM-based, passive parallel asynchronous | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| On-chip PLL | Yes | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant (per distributor listing) |
| Family | — | FLEX 10KE |
| Typical Gates | — | 200,000 |
| Maximum User I/Os | — | 470 |
| Embedded Memory | — | 98,304 bits |
| Embedded Array Blocks (EABs) | — | 12 |
| Package Dimensions | — | 45 x 45 mm |
| Ball Pitch | — | 1.27 mm |
| Propagation Delay | — | 0.4 ns |
| Supply Voltage (Core) | — | [DATA_NEEDED: core Vcc] |
| Programmability | — | JTAG (IEEE 1149.1) / in-system |
| Logic Family | — | CMOS |