EPF10K50EFC484-2 vs EPF10K50VFC484-3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K50EFC484-2 sa pamamagitan ng Altera at EPF10K50VFC484-3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPF10K50EFC484-2 - 50K Gates FLEX-10KE FPGA, 484-BGA | Intel / Altera
EPF10K50EFC484-2 Obsolete
Pagsanggunian na paghahambing
| Parametro | EPF10K50EFC484-2 | EPF10K50VFC484-3N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | FLEX-10KE | FLEX-10K |
| Logic Elements (LEs) | 2,880 | — |
| Typical Gates | 50,000 | 50,000 |
| Embedded Memory (Bits) | 40,960 | — |
| Embedded Array Blocks (EABs) | 12 (each 2,048 bits) | 12 |
| Maximum User I/O Pins | 220 | — |
| Packhaging | 484-ball FineLine BGA (FBGA) | 484-FBGA (23 x 23 mm, 1.27 mm pitch) |
| Process Technology | 0.22 micrometer CMOS | 0.42 µm CMOS, SRAM-based |
| Core Voltage | 2.5 V | — |
| Internal Frequency | 200 MHz | 125 MHz |
| Speed Grade | -2 | — |
| Temperature na Operasyon | 0 C to +70 C (Commercial) | 0 °C to +70 °C (commercial) |
| JTAG Boundary-Scan | IEEE Std. 1149.1-1990 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 at 33/66 MHz (3.3 V); 5.0 V at speed grade -1 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Logic Elements | — | 2,880 |
| Total RAM Bits | — | 40,960 |
| Logic Array Blocks (LABs) | — | 10 |
| Maximum User I/Os | — | 291 |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Voltage Standards | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt) |
| Propagation Delay (per LE) | — | 0.6 ns |
| Configuration Modes | — | Passive Serial, Passive Parallel (Sync/Async), Active Serial, JTAG |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |