EPF6010ANTC100-3 vs EPF6010ANTC100-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF6010ANTC100-3 sa pamamagitan ng Intel at EPF6010ANTC100-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPF6010ANTC100-3 - FLEX 6000 FPGA 880 LE 71 I/O 100-TQFP | Intel
EPF6010ANTC100-3 ⚠ Huling PagbiliIntel
EPF6010ANTC100-2 - FLEX 6000 FPGA, 880 LEs, 71 I/O, 100-TQFP | Intel
EPF6010ANTC100-2 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPF6010ANTC100-3 | EPF6010ANTC100-2 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Family | FLEX 6000 | FLEX 6000 / FLEX 6000A |
| Logic Elements | 880 LE | 880 |
| User I/O Count | 71 | — |
| Embedded Memory | 16000 bit | [DATA_NEEDED: embedded RAM blocks] |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Packhaging | 100-TQFP | 100-pin TQFP (14x14 mm, 0.5 mm pitch) |
| Speed Grade | -3 | -2 |
| Core Voltage | 5 V | — |
| Process Technology | 0.42 µm CMOS SRAM | — |
| Configuration Interface | JTAG (IEEE 1149.1) / Serial / Parallel | — |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| I/O Standards Supported | LVTTL, LVCMOS, PCI (MultiVolt I/O) | TTL, CMOS, PCI (with clamping diodes) |
| Programmable Interconnect | Continuous FastTrack | — |
| Programmable I/O Pins | — | 71 |
| Temperature na Operasyon | — | Commercial (0C to +70C) |
| Configuration Method | — | SRAM (volatile), in-system programmable |
| Programming Interface | — | IEEE 1149.1 (JTAG) / passive serial / EPC configuration device |
| Supply Voltage (VCCINT) | — | 5.0 V (FLEX 6000A); 3.3 V (FLEX 6000) |
| Number of LABs | — | [DATA_NEEDED: LAB count] |
| Global Clock Networks | — | [DATA_NEEDED: global clock count] |
| Level ng MSL | — | 3 (168 hours) |
| Packaging | — | Tray (per Altera packing standard) |