EPF6010ATC100-2 vs EPF6016AFC100-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF6010ATC100-2 sa pamamagitan ng Altera at EPF6016AFC100-3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPF6010ATC100-2 - FLEX 6000 FPGA, 880 Gates, 71 I/O | Intel (Altera)
EPF6010ATC100-2 Obsolete
Pagsanggunian na paghahambing
| Parametro | EPF6010ATC100-2 | EPF6016AFC100-3 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | FLEX 6000 | — |
| Family | SRAM-based FPGA | FLEX 6000 |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements / Gates | 880 gates (typical) | — |
| Logic Array Blocks (LABs) | 88 | — |
| User I/O Pins | 71 | — |
| Number of Logic Cells | 880 (per FLEX 6000 family datasheet) | — |
| Packhaging | 100-pin TQFP (14x14 mm) | 100-pin FineLine BGA (FBGA) |
| Speed Grade | -2 | — |
| Temperature na Operasyon | 0C to 70C (commercial) | 0 C to 85 C (Commercial) |
| Core Supply Voltage | 3.0 V to 3.6 V (typical 3.3 V) | — |
| I/O Supply Voltage | 3.3 V (5 V tolerant inputs per FLEX 6000 family) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial configuration | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | unknown |
| Process Node | [DATA_NEEDED: CMOS process node] | — |
| Total RAM Bits | [DATA_NEEDED: embedded RAM] | — |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Gates | — | 16,000 gates |
| Logic Cells | — | 1,320 cells |
| Maximum Internal Frequency | — | 142.86 MHz |
| Process Technology | — | 0.42 um CMOS |
| User I/O | — | 81 |
| Volte ng Pagbibigay | — | 3.3 V |
| Architecture | — | SRAM-based, 4-input LUT |
| Configuration Method | — | SRAM (in-system programmable) |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |