EPF6016ATI144-3N vs EPF6016TC144-3U Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF6016ATI144-3N sa pamamagitan ng Altera at EPF6016TC144-3U sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPF6016ATI144-3N - FLEX 6000 FPGA 16K Gates 117 I/O | Altera / Intel
EPF6016ATI144-3N ⚠ Huling PagbiliAltera
EPF6016TC144-3U - FLEX 6000 FPGA 16K Gates 1320 Cells TQFP-144 | Altera
EPF6016TC144-3U ObsoletePagsanggunian na paghahambing
| Parametro | EPF6016ATI144-3N | EPF6016TC144-3U |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | FLEX 6000 | FLEX 6000 |
| Logic Elements | 1,320 | — |
| Logic Array Blocks (LABs) | 132 | — |
| Equivalent Gates | 16,000 | — |
| User I/O | 117 | — |
| Dedicated Inputs | 4 | — |
| Packhaging | 144-pin TQFP (LQFP-144) | TQFP-144 (TC144), 0.5 mm pitch |
| Process Technology | 0.42 µm CMOS, SRAM | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Internal Frequency | 142.86 MHz max | 172 MHz (max) |
| Temperature na Operasyon | -40 °C to +85 °C (industrial) | [DATA_NEEDED: industrial range from 'U' suffix] |
| Speed Grade | -3 | -3 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration | SRAM, in-system programmable via JTAG | — |
| Lead-Free / RoHS | Yes (N suffix) | — |
| JTAG Support | IEEE 1149.1 boundary scan | — |
| Series | — | EPF6016 |
| Device Type | — | FPGA - Field Programmable Gate Array |
| Logic Elements (LEs) | — | 1320 |
| Total Logic Cells | — | 1320 |
| Typical Gates | — | 16000 |
| Maximum Gates | — | 24000 |
| User I/Os | — | 117 |
| Bilang ng Pin | — | 144 |
| Pin-to-Pin Logic Delay | — | 4 ns (speed grade -3) |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCCINT and VCCIO values] |
| Tindminan RoHS | — | Compliant (verified by 'U' suffix marking convention) |
| Configuration Method | — | SRAM-based, EPC1/EPC2 PROM or JTAG (IEEE 1149.1) |