EPF8820ARI208-1 vs EPF8820ARC208-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF8820ARI208-1 sa pamamagitan ng Altera at EPF8820ARC208-3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 ObsoletePagsanggunian na paghahambing
| Parametro | EPF8820ARI208-1 | EPF8820ARC208-3 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | FLEX 8000 | FLEX 8000 (EPF8820) |
| Technology | SRAM-based, 0.42 µm CMOS | — |
| Usable Gates | 8,000 | 8,000 |
| Logic Elements (LEs) | 672 | — |
| Flip-Flops | 820 | — |
| Maximum User I/O | 152 | — |
| Embedded Memory | [DATA_NEEDED: embedded memory bits] | — |
| Supply Voltage (VCCINT) | 5 V nominal (4.5 V to 5.5 V) | — |
| I/O Voltage Standards | 3.3 V or 5 V configurable | — |
| Maximum Toggle Frequency | 125 MHz | — |
| Packhaging | 208-pin RQFP | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40 °C to +85 °C (industrial) | — |
| Configuration Interface | JTAG / IEEE 1149.1 + serial/parallel EPROM | — |
| Process Geometry | 0.42 µm | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Series | — | FLEX 8000 |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Process Technology | — | 0.42 µm CMOS |
| Configuration Memory | — | SRAM (volatile) |
| Packhaging / Kaso | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| Packaging | — | Tray |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |