EPM1270F256C5 vs EPM1270F256I5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM1270F256C5 sa pamamagitan ng Altera at EPM1270F256I5 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM1270F256C5 - MAX II 980 Macrocell CPLD | Altera / Intel | 256-FBGA
EPM1270F256C5 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM1270F256C5 | EPM1270F256I5 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | EPM1270 |
| Family | EPM1270 | — |
| Macro Cells | 980 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 212 | — |
| Pin-to-Pin Logic Delay (tPD) | 6.2 ns (C5 speed grade) | — |
| Internal Operating Frequency | 201.1 MHz | — |
| Core Supply Voltage | 2.5 V / 3.3 V | — |
| I/O Standards Supported | LVCMOS/LVTTL 1.8 V, 2.5 V, 3.3 V, 5.0 V (MultiVolt) | — |
| Process Technology | 0.18 µm | 0.18 µm |
| Configuration Memory | On-chip flash (non-volatile, instant-on) | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Programming Interface | JTAG (IEEE 1149.1) / ISP via ByteBlaster / USB-Blaster | JTAG (IEEE 1149.1) / ISP |
| Packhaging | 256-ball FineLine BGA (FBGA-256) | 256-ball FBGA (FineLine BGA) |
| Temperature na Operasyon | 0 °C to +85 °C (commercial, 'C' grade) | -40 °C to +100 °C (industrial, "I") |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX II |
| Macrocell Count | — | 980 |
| Logic Elements | — | 1270 |
| User I/O Pins | — | 212 (max) |
| Pin/Package Count | — | 256 |
| Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V |
| Maximum Internal Frequency | — | 201.1 MHz |
| Pin-to-Pin Delay (tPD) | — | 6.2 ns |
| Speed Grade | — | 5 |
| Uri ng Pagpapasok | — | Surface Mount |