EPM1270F256I5N vs EPM2210F256I5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM1270F256I5N sa pamamagitan ng Intel at EPM2210F256I5 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM1270F256I5N - 980-Macrocell MAX II CPLD, 256-FBGA | Intel / Altera
EPM1270F256I5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM1270F256I5N | EPM2210F256I5 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | MAX II CPLD |
| Family | MAX II (EPM1270) | MAX II |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 980 | — |
| Logic Elements | 1270 | — |
| User I/O Pins | 212 | — |
| User Flash Memory | 8 Kbits | 8 Kbit |
| Maximum Operating Frequency | 201.1 MHz | — |
| Pin-to-Pin Logic Delay | 6.2 ns (I5 speed grade) | — |
| External Supply Voltage | 2.5 V / 3.3 V | — |
| Internal Core Voltage | 1.8 V (on-chip regulator) | — |
| I/O Bank Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) + 3.3 V PCI-compliant bank | — |
| Process Technology | 0.18-micron Flash-based CMOS | — |
| Configuration Memory | Non-volatile Flash (instant-on) | — |
| Programming Interface | JTAG IEEE 1149.1 (boundary-scan + ISP) | — |
| Packhaging | 256-ball FBGA (FineLine BGA), 17 x 17 mm | — |
| Temperature na Operasyon | -40C to +100C (TJ), industrial | — |
| Speed Grade | I5 (industrial, 6.2 ns tPD) | — |
| Uri ng Pagpapasok | Surface Mount (SMT, BGA) | Surface Mount |
| Tindminan RoHS | Compliant | Non-compliant (contains lead, per IC Components datasheet) |
| Wala sa Halogen | Compliant (per GlobalSpec) | — |
| Country of Origin | Malaysia / Republic of Korea | — |
| Number of Macrocells | — | 1700 |
| Number of Logic Elements | — | 2210 |
| Maximum Internal Frequency | — | 201.1 MHz |
| Maximum Propagation Delay (tpd) | — | 7.0 ns |
| Supply Voltage - Internal | — | 2.5 V, 3.3 V |
| Operating Temperature (TJ) | — | -40 C to +100 C |
| Packhaging / Kaso | — | 256-FBGA (17x17) |
| Programmable I/O Pins | — | [DATA_NEEDED: number of user I/O pins] |
| Number of Logic Array Blocks | — | 16 |
| I/O Voltage Standards | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| JTAG Compliant | — | Yes (IEEE 1149.1) |
| In-System Programmable | — | Yes (via ByteBlaster/USB-Blaster) |
| Delivery Type | — | Tray |