EPM240GM100C5N vs EPM240M100C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240GM100C5N sa pamamagitan ng Altera at EPM240M100C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM240GM100C5N - 192-Cell MAX II G CPLD, 4.7ns, 100-MBGA | Intel / Altera
EPM240GM100C5N ✓ NakahandaIntel
EPM240M100C4N - 192 Macrocell MAX II CPLD, 100-MBGA | Intel / Altera
EPM240M100C4N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM240GM100C5N | EPM240M100C4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II G | — |
| Logic Elements | 240 (192 macrocells) | — |
| User I/Os | 80 | 80 |
| Pin-to-Pin Delay (tPD) | 4.7 ns | — |
| Packhaging | 100-MBGA (Micro FineLine BGA), 6 x 6 mm | 100-pin Micro FineLine BGA (MBGA), 6 x 6 mm, 0.5 mm pitch |
| Ball Pitch | 0.5 mm | — |
| Supply Voltage - Core | 3.3 V | 2.5 V / 3.3 V |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multiVolt) | — |
| Programming Interface | JTAG (IEEE 1149.1) - ISP | — |
| Configuration Memory | Non-volatile Flash | Non-volatile on-chip flash (instant-on) |
| Temperature na Operasyon | -40 C to +125 C | -40 C to +125 C (industrial) |
| Lead Free / RoHS | Yes / Compliant | — |
| Level ng MSL | 3 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Process Technology | CMOS, Flash-based | — |
| Series | — | MAX II |
| Device Family | — | EPM240 |
| Macro Cells | — | 192 |
| Propagation Delay (tPD) Max | — | 4.7 ns |
| Internal Operating Frequency | — | 247.5 MHz |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| User Flash Memory | — | 8 Kbit |
| Programmability | — | In-System Programmable via JTAG (IEEE 1149.1) |
| Logic Family | — | CMOS |
| Tindminan RoHS | — | Lead Free (per DigiChip spec sheet) |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells per LAB) |
| MultiTrack Interconnect | — | Yes |
| Hot Socketing | — | Yes |