EPM240M100C5N vs EPM240F100C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240M100C5N sa pamamagitan ng Intel at EPM240F100C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM240M100C5N | EPM240F100C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Family | MAX II | — |
| Logic Elements | 240 | — |
| Macrocells | 192 | 192 |
| User I/Os | 80 | — |
| Propagation Delay (tPD) | 4.7 ns | — |
| User Flash Memory | 8 Kbits | — |
| Supply Voltage - Core | 1.8 V | — |
| Supply Voltage - I/O | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Temperature na Operasyon | -40 C to +125 C | — |
| Packhaging | 100-ball MBGA (Micro FBGA), 6 x 6 mm, 0.5 mm pitch | 100-ball FineLine BGA (FBGA-100) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Process Technology | 0.18 µm CMOS | — |
| Configuration Memory | On-chip Flash (non-volatile) | Non-volatile flash (instant-on) |
| JTAG Support | IEEE 1149.1 boundary-scan | IEEE 1149.1 boundary-scan |
| Tindminan RoHS | Compliant (lead-free) | Compliant |
| Logic Family | CMOS | — |
| Device Family | — | MAX II |
| Logic Elements (LEs) | — | 240 |
| User I/O Pins (maximum) | — | 80 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.7 ns |
| Maximum Operating Frequency | — | [DATA_NEEDED: fmax per datasheet] |
| Global Clock Networks | — | [DATA_NEEDED: count] |
| Hanay ng Temperature na Operasyon | — | 0C to +85C (commercial) |
| Supply Voltage Core (VCCINT) | — | 3.3 V |
| I/O Bank Voltage (VCCIO) | — | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) |
| Programming Interface | — | JTAG / ByteBlasterMV |