EPM240T100C4N vs EPM240T100A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240T100C4N sa pamamagitan ng Altera at EPM240T100A5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM240T100A5N - 192-Macrocell MAX II CPLD, 100-TQFP | Intel / Altera
EPM240T100A5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM240T100C4N | EPM240T100A5N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | MAX II |
| Device | EPM240 | — |
| Macro Cells | 192 | 192 |
| Logic Elements | 240 | — |
| Propagation Delay (tPD) | 4.7 ns (max) | — |
| Maximum Frequency | 247.5 MHz | — |
| User I/O | 80 | — |
| Supply Voltage - Internal | 2.5 V / 3.3 V | — |
| I/O Voltage (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm | 0.18 µm |
| Programmable Type | In-System Programmable (Flash) | — |
| Packhaging / Kaso | 100-TQFP | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0 °C to +85 °C (commercial, 'C' suffix) | 0C to +85C (commercial, "A5N" suffix) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tindminan RoHS | Compliant (lead-free, 'N' suffix) | Compliant (Pb-free) |
| Logic Elements (LE) | — | 240 |
| User I/O Count | — | 80 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Volte ng Pagbibigay | — | 2.5 V / 3.3 V |
| I/O Bank Count | — | 4 (multi-voltage) |
| Configuration Memory | — | On-chip Flash (instant-on) |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Packhaging | — | 100-pin TQFP (14 x 14 x 1.0 mm) |