EPM240T100C4N vs EPM240T100C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240T100C4N sa pamamagitan ng Altera at EPM240T100C3N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM240T100C4N | EPM240T100C3N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | — |
| Device | EPM240 | — |
| Macro Cells | 192 | — |
| Logic Elements | 240 | — |
| Propagation Delay (tPD) | 4.7 ns (max) | — |
| Maximum Frequency | 247.5 MHz | — |
| User I/O | 80 | — |
| Supply Voltage - Internal | 2.5 V / 3.3 V | — |
| I/O Voltage (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm | — |
| Programmable Type | In-System Programmable (Flash) | — |
| Packhaging / Kaso | 100-TQFP | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0 °C to +85 °C (commercial, 'C' suffix) | 0 °C to +85 °C (commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tindminan RoHS | Compliant (lead-free, 'N' suffix) | Compliant |
| Series | — | MAX II |
| Device Family | — | MAX II CPLD (EPM240) |
| Logic Elements (LE) | — | 240 |
| Macrocells | — | 192 |
| User I/O Pins | — | 80 |
| User Flash Memory (UFM) | — | 8 Kbits |
| Packhaging | — | 100-pin TQFP (14x14 mm) |
| Configuration Memory | — | Internal Flash (non-volatile) |
| Pin-to-Pin Logic Delay (tPD) | — | 4.4 ns (typical) |
| Maximum Operating Frequency | — | 200 MHz (internal oscillator) |
| Core Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Quiescent Current (typical) | — | 35 mA |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |