EPM240ZM100C6N vs EPM240M100C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240ZM100C6N sa pamamagitan ng Intel at EPM240M100C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM240M100C4N - 192 Macrocell MAX II CPLD, 100-MBGA | Intel / Altera
EPM240M100C4N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM240ZM100C6N | EPM240M100C4N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | — |
| Logic Elements | 240 | — |
| Macro Cells | 192 | 192 |
| User I/Os | 80 | 80 |
| Propagation Delay (tPD) | 7.5 ns | — |
| Max Internal Frequency | 184.1 MHz | — |
| Global Clocks | 4 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Process Technology | 0.18 µm 6-layer-metal flash | — |
| Core Supply Voltage | 1.8 V | — |
| I/O Supply Voltages (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V | — |
| Standby Current | 25 µA typical | — |
| Packhaging | 100-MBGA (Micro FineLine BGA), 6 × 6 mm, 0.5 mm pitch | 100-pin Micro FineLine BGA (MBGA), 6 x 6 mm, 0.5 mm pitch |
| Temperature na Operasyon | -40 °C to +125 °C | -40 C to +125 C (industrial) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Programming | JTAG ISP (in-system programmable) | — |
| Lead Free | Yes | — |
| Series | — | MAX II |
| Device Family | — | EPM240 |
| Propagation Delay (tPD) Max | — | 4.7 ns |
| Internal Operating Frequency | — | 247.5 MHz |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| User Flash Memory | — | 8 Kbit |
| Programmability | — | In-System Programmable via JTAG (IEEE 1149.1) |
| Configuration Memory | — | Non-volatile on-chip flash (instant-on) |
| Logic Family | — | CMOS |
| Tindminan RoHS | — | Lead Free (per DigiChip spec sheet) |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells per LAB) |
| MultiTrack Interconnect | — | Yes |
| Hot Socketing | — | Yes |