EPM3032A-TC44-10 vs EPM3032ALC44-4 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3032A-TC44-10 sa pamamagitan ng Altera at EPM3032ALC44-4 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3032A-TC44-10 EPM3032ALC44-4
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 3000A MAX 3000A
Macrocells 32 32
Logic Array Blocks 2 —
User I/O Pins 34 34
Logic Gates 600 —
Propagation Delay (tPD) 10 ns —
Maximum Internal Frequency 227.3 MHz —
Supply Voltage (VCCINT/VCCIO) 3.0 V to 3.6 V (typ. 3.3 V) —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Output Enables 6 —
Configuration Memory CMOS EEPROM (non-volatile) —
Packhaging TQFP-44 44-pin PLCC (J-Lead)
Uri ng Pagpapasok Surface Mount Surface Mount (PLCC J-Lead)
Operating Temperature (Commercial) 0 °C to +70 °C —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Process Technology CMOS EEPROM —
Logic Array Blocks (LABs) — 2
Pin-to-Pin Delay (tPD) — 4.5 ns
Maximum Counter Frequency — 227.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V (MultiVolt: 5.0 V / 3.3 V / 2.5 V compatible)
Usable Gates — 600 to 10,000 (MAX 3000A family range)
Temperature na Operasyon — 0°C to +70°C (Commercial)
Technology — CMOS EEPROM-based
In-System Programmability (ISP) — Yes, IEEE Std. 1532 compliant
Boundary-Scan Test — IEEE Std. 1149.1 (JTAG)
Programming Interface — JTAG (ByteBlaster / MasterBlaster)

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