EPM3032ALC44-10N vs EPM3032ALC44-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3032ALC44-10N sa pamamagitan ng Altera at EPM3032ALC44-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3032ALC44-10 - MAX 3000A CPLD, 32 Macrocells, 10ns, 44-PLCC | Intel / Altera
EPM3032ALC44-10 ObsoletePagsanggunian na paghahambing
| Parametro | EPM3032ALC44-10N | EPM3032ALC44-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 600 gates | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 34 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal fMAX | 103.1 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| Technology | CMOS EEPROM-based | — |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| ISP Standard Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Yes, IEEE 1149.1 compliant | — |
| Packhaging | 44-pin PLCC (J-Lead, surface mount) | 44-pin PLCC (J-Lead) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount / Socket |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial range] | 0C to +70C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: compliant or non-compliant] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 600 |
| Maximum User I/O Pins | — | 34 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| In-System Programming | — | Yes - JTAG (IEEE Std. 1149.1) |
| Concurrent ISP | — | Yes - IEEE Std. 1532 |
| Process Technology | — | CMOS EEPROM |