EPM3032ALC44-10N vs EPM3032ATI44-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3032ALC44-10N sa pamamagitan ng Altera at EPM3032ATI44-10N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3032ALC44-10N EPM3032ATI44-10N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Logic Gates 600 gates —
Macrocells 32 —
Logic Array Blocks (LABs) 2 —
User I/O Pins 34 —
Propagation Delay (tPD) 10 ns —
Internal fMAX 103.1 MHz —
Supply Voltage (VCCINT) 3.3 V 3.0 V to 3.6 V (3.3 V typical)
I/O Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) —
Technology CMOS EEPROM-based —
In-System Programmability Yes, via IEEE 1149.1 JTAG —
ISP Standard Compliance IEEE Std. 1532 —
Boundary-Scan Test (BST) Yes, IEEE 1149.1 compliant —
Packhaging 44-pin PLCC (J-Lead, surface mount) —
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon [DATA_NEEDED: industrial/commercial range] -40C to +85C (industrial, 'I' grade)
Tindminan RoHS [DATA_NEEDED: compliant or non-compliant] RoHS Non-Compliant (contains lead)
Logic Capacity — 600 usable gates
Number of Macrocells — 32
Number of User I/Os — 34
Packhaging / Kaso — TQFP-44 (10x10 mm, 0.8 mm pitch)
MultiVolt I/O Interface — 5.0 V, 3.3 V, 2.5 V compatible
Pin-to-Pin Delay (tPD) — 10 ns
Counter Frequency (fCNT) — 103.1 MHz
Setup Time (tSU) — [DATA_NEEDED: setup time]
Programmability — In-System Programmable (ISP) via IEEE Std. 1149.1 JTAG
ISP Standard — IEEE Std. 1532 compliant
Configuration Memory — Non-volatile EEPROM
Hot-Socketing Support — Yes
Lead-Free Status — Contains lead

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