EPM3032ALC44-7 vs EPM3032ALC44-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3032ALC44-7 sa pamamagitan ng Altera at EPM3032ALC44-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3032ALC44-7 EPM3032ALC44-10N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Logic Elements / Macrocells 32 macrocells —
Logic Array Blocks (LABs) 2 2
System Gates 600 —
Number of User I/O Pins 34 —
Global Clocks 2 —
Propagation Delay (tPD1, max) 7.5 ns —
Maximum Internal Frequency (fMAX) 138.9 MHz —
Supply Voltage (VCCINT / VCCIO) 3.3 V —
I/O Tolerant Voltage 2.5 V / 3.3 V / 5.0 V (MultiVolt) —
Program Memory Type EEPROM —
In-System Programming (ISP) Yes - IEEE 1149.1 JTAG —
Temperature na Operasyon 0 °C to +70 °C (Commercial) [DATA_NEEDED: industrial/commercial range]
Packhaging 44-pin PLCC (J-Lead), 16.59 x 16.59 mm, 3.81 mm height 44-pin PLCC (J-Lead, surface mount)
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS Not Compliant (per Arrow listing) [DATA_NEEDED: compliant or non-compliant]
Part Status Obsolete —
ECCN EAR99 —
Product Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 600 gates
Macrocells — 32
User I/O Pins — 34
Propagation Delay (tPD) — 10 ns
Internal fMAX — 103.1 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O)
Technology — CMOS EEPROM-based
In-System Programmability — Yes, via IEEE 1149.1 JTAG
ISP Standard Compliance — IEEE Std. 1532
Boundary-Scan Test (BST) — Yes, IEEE 1149.1 compliant

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