EPM3064ALC44-10N vs EPM3064ATC44-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ALC44-10N sa pamamagitan ng Altera at EPM3064ATC44-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM3064ATC44-10N EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N ✓ Nakahanda

Pagsanggunian na paghahambing

Parametro EPM3064ALC44-10N EPM3064ATC44-10N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Aktibo
Product Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 64 —
Logic Array Blocks (LABs) 4 4
User I/O Pins 34 34
Usable Gates 1,250 1250
Propagation Delay (tPD) 10 ns —
Maximum Counter Frequency 227.3 MHz 192.3 MHz
Supply Voltage (VCCINT) 3.0 V to 3.6 V 3.3 V
I/O Bank Voltage (VCCIO) 3.0 V to 3.6 V (MultiVolt) —
Configuration Memory CMOS EEPROM EEPROM (non-volatile)
In-System Programmability Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) —
Packhaging 44-pin PLCC (LC44) TQFP-44 (10x10 mm)
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Surface Mount
Temperature na Operasyon [DATA_NEEDED: commercial / industrial grade] 0C to +70C (commercial)
Tindminan RoHS Compliant Compliant
Open-Drain Output Option Yes (per I/O pin) —
Output Slew-Rate Control Programmable —
Family — MAX 3000A
Macro Cells — 64
Pin-to-Pin Delay (tPD) — 10 ns
I/O Standard — MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V)
In-System Programming — IEEE Std. 1532 compliant
Boundary-Scan Test — IEEE Std. 1149.1 (JTAG) compliant
Pin-Locking — Yes (across design iterations)

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