EPM3064ALC44-7N vs EPM3032ALC44-7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ALC44-7N sa pamamagitan ng Intel at EPM3032ALC44-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3064ALC44-7N - 64-Macrocell MAX 3000A CPLD, 7.5ns, 44-PLCC | Intel / Altera
EPM3064ALC44-7N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM3064ALC44-7N | EPM3032ALC44-7N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | MAX 3000A | — |
| Logic IC Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 2 | — |
| Usable Gates | 1,250 | — |
| Number of User I/O Pins | 34 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Frequency | 135.1 MHz | — |
| Core Technology | CMOS EEPROM | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Tolerance | 5 V-tolerant | — |
| In-System Programmability | Yes (IEEE Std 1149.1 JTAG) | — |
| Packhaging | 44-pin PLCC | 44-PLCC (J-Lead, 16.59 x 16.59 mm) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial grade) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Programming Software | Quartus II / Quartus Prime (legacy MAX+PLUS II supported) | — |
| Manufacturer | — | Altera (Intel) |
| Series | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 32 |
| Logic Gates | — | 600 usable gates |
| Propagation Delay (tPD1) | — | 7.5 ns (max, pin-to-pin) |
| Internal Counter Frequency (fCNT) | — | 227.3 MHz (max) |
| Number of Logic Elements / Blocks | — | 2 LABs (16 macrocells each) |
| Number of I/O Pins | — | 34 usable I/O (44 total package pins) |
| Number of Dedicated Inputs | — | 4 |
| Programmable Type | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Uri ng Memory | — | EEPROM (non-volatile, 100 program/erase cycles) |
| Supply Voltage - Internal (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Bank Voltage (VCCIO) | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Level ng MSL | — | 3 (168 hours) |
| Process Technology | — | CMOS EEPROM |