EPM3064ALC44-7N vs EPM3064ALC44-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ALC44-7N sa pamamagitan ng Intel at EPM3064ALC44-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3064ALC44-7N - 64-Macrocell MAX 3000A CPLD, 7.5ns, 44-PLCC | Intel / Altera
EPM3064ALC44-7N ⚠ Huling PagbiliAltera
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N ObsoletePagsanggunian na paghahambing
| Parametro | EPM3064ALC44-7N | EPM3064ALC44-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | MAX 3000A | — |
| Logic IC Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 2 | 4 |
| Usable Gates | 1,250 | 1,250 |
| Number of User I/O Pins | 34 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Frequency | 135.1 MHz | — |
| Core Technology | CMOS EEPROM | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.0 V to 3.6 V |
| I/O Tolerance | 5 V-tolerant | — |
| In-System Programmability | Yes (IEEE Std 1149.1 JTAG) | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) |
| Packhaging | 44-pin PLCC | 44-pin PLCC (LC44) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: commercial / industrial grade] |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Programming Software | Quartus II / Quartus Prime (legacy MAX+PLUS II supported) | — |
| Product Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/O Pins | — | 34 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| I/O Bank Voltage (VCCIO) | — | 3.0 V to 3.6 V (MultiVolt) |
| Configuration Memory | — | CMOS EEPROM |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Output Slew-Rate Control | — | Programmable |