EPM3064ATC100-10N vs EPM3064AT100-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC100-10N sa pamamagitan ng Altera at EPM3064AT100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC100-10N EPM3064AT100-10N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 64 64
Logic Array Blocks (LABs) 2 4
Maximum User I/O Pins 66 —
Usable Gates 1,250 1,250
Pin-to-Pin Delay (tPD) 10 ns —
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) 3.3 V
In-System Programmability Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 —
Boundary-Scan Test (BST) Yes - JTAG compliant IEEE Std. 1149.1 compliant
Configuration Memory Non-volatile EEPROM EEPROM (non-volatile)
Program/Erase Cycles 100 minimum —
MultiVolt I/O Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant —
Temperature na Operasyon 0C to +70C (commercial) —
Packhaging 100-pin TQFP TQFP-100 (T100), 14 mm x 14 mm
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS Compliant (lead-free) [DATA_NEEDED: RoHS compliance status]
User I/O Pins — 66
Speed Grade — -10 (10 ns pin-to-pin delay)
I/O Bank Voltage — 3.3 V
5 V Tolerant Inputs — Yes (via clamping diodes)
Programming Interface — JTAG (IEEE Std. 1149.1) with pin-locking
ISP Compliance — IEEE Std. 1532
Operating Temperature (Commercial) — 0C to +70C
Lead-Free — [DATA_NEEDED: lead-free finish]

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