EPM3064ATC100-10N vs EPM3064ATC100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC100-10N sa pamamagitan ng Altera at EPM3064ATC100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC100-10N EPM3064ATC100-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 64
Logic Array Blocks (LABs) 2 —
Maximum User I/O Pins 66 —
Usable Gates 1,250 —
Pin-to-Pin Delay (tPD) 10 ns —
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) 3.3 V
In-System Programmability Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant
Boundary-Scan Test (BST) Yes - JTAG compliant —
Configuration Memory Non-volatile EEPROM —
Program/Erase Cycles 100 minimum —
MultiVolt I/O Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant —
Temperature na Operasyon 0C to +70C (commercial) —
Packhaging 100-pin TQFP TQFP-100 (100-pin Thin Quad Flat Pack)
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS Compliant (lead-free) [DATA_NEEDED: RoHS compliance]
Logic Gates — 1250 gates
Logic Array Blocks — 2
User I/O Pins — 34
Propagation Delay (tPD) — 10 ns
Process Technology — CMOS EEPROM
Global Clock Signals — 2 (with optional inversion)
Output Enable Signals — 6 or 10 pin- or logic-driven
Output Slew-Rate Control — Programmable
Operating Temperature Grade — Commercial
MultiVolt I/O Support — 1.5V / 1.8V / 2.5V / 3.3V interfaces

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