EPM3064ATC100-4N vs EPM3064ATC100-7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC100-4N sa pamamagitan ng Altera at EPM3064ATC100-7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC100-4N EPM3064ATC100-7
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 64 —
Logic Array Blocks 2 —
Usable Gates 1,250 1,250
User I/O Pins 66 —
Pin-to-Pin Delay (tPD) 4.5 ns —
Counter Frequency 222.2 MHz (max) —
Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V —
Packhaging 100-pin TQFP 100-pin TQFP
Uri ng Pagpapasok Surface Mount Surface Mount
Programming Interface IEEE Std. 1149.1 JTAG (ISP) —
ISP Standard IEEE Std. 1532 —
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C (commercial)
Process Technology CMOS EEPROM —
Tindminan RoHS [DATA_NEEDED: RoHS status] —
Macrocells — 64
Logic Array Blocks (LABs) — 2
Maximum User I/Os — 66 (in 100-pin TQFP)
Pin-to-Pin Propagation Delay (tPD) — 7.5 ns (-7 speed grade)
Maximum Internal Counter Frequency — 135.1 MHz
Supply Voltage - VCCINT (Core) — 3.3 V
Supply Voltage - VCCIO (I/O) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
Technology — CMOS EEPROM
In-System Programming (ISP) — Yes, via IEEE 1149.1 JTAG
PCI Compliance — PCI Local Bus Specification Revision 2.2
JTAG Boundary Scan — Yes
Lead Free / RoHS — Compliant (modern shipments)

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