EPM3064ATC100-4N vs EPM3064ATC100-7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC100-4N sa pamamagitan ng Altera at EPM3064ATC100-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3064ATC100-4N | EPM3064ATC100-7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 64 | — |
| Logic Array Blocks | 2 | — |
| Usable Gates | 1,250 | up to 1,250 |
| User I/O Pins | 66 | 66 |
| Pin-to-Pin Delay (tPD) | 4.5 ns | — |
| Counter Frequency | 222.2 MHz (max) | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | 3.3 V or 2.5 V |
| Packhaging | 100-pin TQFP | TQFP-100 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| ISP Standard | IEEE Std. 1532 | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| Process Technology | CMOS EEPROM | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirmed RoHS status from manufacturer page] |
| Macrocells | — | 64 |
| Logic Array Blocks (LABs) | — | 2 |
| Propagation Delay (tPD) | — | 7.5 ns (pin-to-pin, -7 speed grade) |
| Maximum Internal Frequency | — | 166.7 MHz (-7 speed grade) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| Program Memory Technology | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 |