EPM3064ATC100-4N vs EPM3064ATI100-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC100-4N sa pamamagitan ng Altera at EPM3064ATI100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC100-4N EPM3064ATI100-10N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Aktibo
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 64 —
Logic Array Blocks 2 —
Usable Gates 1,250 1,250
User I/O Pins 66 —
Pin-to-Pin Delay (tPD) 4.5 ns 10 ns (-10 speed grade)
Counter Frequency 222.2 MHz (max) —
Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V —
Packhaging 100-pin TQFP 100-pin TQFP (industrial)
Uri ng Pagpapasok Surface Mount —
Programming Interface IEEE Std. 1149.1 JTAG (ISP) —
ISP Standard IEEE Std. 1532 —
Temperature na Operasyon 0C to +70C (commercial) -40 C to +85 C (industrial)
Process Technology CMOS EEPROM —
Tindminan RoHS [DATA_NEEDED: RoHS status] RoHS Non-Compliant
Programmable Type — In-System Programmable (ISP) via IEEE 1149.1 JTAG
Technology — CMOS EEPROM
Macrocells — 64
Logic Array Blocks (LABs) — 4
User I/O — 66
Supply Voltage (Core / I/O) — 3.3 V
Maximum Internal Frequency — 227.3 MHz (counter)
JTAG (IEEE 1149.1) — Yes
PCI Compliance — PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades)
MultiVolt I/O — Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing
Lead-Free Status — Contains Lead

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