EPM3064ATC100-7 vs EPM3064ATC100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC100-7 sa pamamagitan ng Altera at EPM3064ATC100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC100-7 EPM3064ATC100-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 3000A MAX 3000A
Usable Gates 1,250 —
Macrocells 64 64
Logic Array Blocks (LABs) 2 —
Maximum User I/Os 66 (in 100-pin TQFP) —
Pin-to-Pin Propagation Delay (tPD) 7.5 ns (-7 speed grade) —
Maximum Internal Counter Frequency 135.1 MHz —
Supply Voltage - VCCINT (Core) 3.3 V —
Supply Voltage - VCCIO (I/O) 2.5 V or 3.3 V (5.0 V tolerant inputs) —
Technology CMOS EEPROM —
Packhaging 100-pin TQFP TQFP-100 (100-pin Thin Quad Flat Pack)
Uri ng Pagpapasok Surface Mount —
Temperature na Operasyon 0C to +70C (commercial) —
In-System Programming (ISP) Yes, via IEEE 1149.1 JTAG —
PCI Compliance PCI Local Bus Specification Revision 2.2 —
JTAG Boundary Scan Yes —
Lead Free / RoHS Compliant (modern shipments) —
Logic Gates — 1250 gates
Logic Array Blocks — 2
User I/O Pins — 34
Propagation Delay (tPD) — 10 ns
Supply Voltage (VCCINT) — 3.3 V
Process Technology — CMOS EEPROM
In-System Programmability — IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant
Global Clock Signals — 2 (with optional inversion)
Output Enable Signals — 6 or 10 pin- or logic-driven
Output Slew-Rate Control — Programmable
Operating Temperature Grade — Commercial
MultiVolt I/O Support — 1.5V / 1.8V / 2.5V / 3.3V interfaces
Tindminan RoHS — [DATA_NEEDED: RoHS compliance]

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