EPM3064ATC100-7 vs EPM3064ATC100-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC100-7 sa pamamagitan ng Altera at EPM3064ATC100-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC100-7 EPM3064ATC100-7N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 3000A MAX 3000A
Usable Gates 1,250 up to 1,250
Macrocells 64 64
Logic Array Blocks (LABs) 2 2
Maximum User I/Os 66 (in 100-pin TQFP) —
Pin-to-Pin Propagation Delay (tPD) 7.5 ns (-7 speed grade) —
Maximum Internal Counter Frequency 135.1 MHz —
Supply Voltage - VCCINT (Core) 3.3 V —
Supply Voltage - VCCIO (I/O) 2.5 V or 3.3 V (5.0 V tolerant inputs) —
Technology CMOS EEPROM —
Packhaging 100-pin TQFP TQFP-100
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon 0C to +70C (commercial) 0 °C to +70 °C (commercial)
In-System Programming (ISP) Yes, via IEEE 1149.1 JTAG —
PCI Compliance PCI Local Bus Specification Revision 2.2 —
JTAG Boundary Scan Yes —
Lead Free / RoHS Compliant (modern shipments) —
Device Type — CPLD - Complex Programmable Logic Device
User I/O Pins — 66
Propagation Delay (tPD) — 7.5 ns (pin-to-pin, -7 speed grade)
Maximum Internal Frequency — 166.7 MHz (-7 speed grade)
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
Program Memory Technology — EEPROM (non-volatile)
In-System Programming — IEEE Std. 1149.1 (JTAG), IEEE Std. 1532
Tindminan RoHS — [DATA_NEEDED: confirmed RoHS status from manufacturer page]

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