EPM3064ATI100-10 vs EPM3064ATC100-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI100-10 sa pamamagitan ng Intel at EPM3064ATC100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3064ATC100-10N - MAX 3000A CPLD, 64 Macrocells, 66 I/O | Altera
EPM3064ATC100-10N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3064ATI100-10 | EPM3064ATC100-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 64 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of User I/Os | 66 | — |
| Usable Gates | 1,250 | 1,250 |
| Volte ng Pagbibigay | 3.3 V | — |
| Speed Grade | -10 (10 ns pin-to-pin) | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Packhaging | 100-pin TQFP | 100-pin TQFP |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Operating Temperature Grade | Industrial | — |
| Lead Free Status | Contains Lead | — |
| Tindminan RoHS | Non-Compliant | Compliant (lead-free) |
| Macrocells | — | 64 |
| Logic Array Blocks (LABs) | — | 2 |
| Maximum User I/O Pins | — | 66 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| In-System Programmability | — | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Yes - JTAG compliant |
| Configuration Memory | — | Non-volatile EEPROM |
| Program/Erase Cycles | — | 100 minimum |
| MultiVolt I/O | — | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |
| Temperature na Operasyon | — | 0C to +70C (commercial) |