EPM3064ATI100-10N vs EPM3064ATC100-4N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI100-10N sa pamamagitan ng Altera at EPM3064ATC100-4N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATI100-10N EPM3064ATC100-4N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Programmable Type In-System Programmable (ISP) via IEEE 1149.1 JTAG —
Technology CMOS EEPROM —
Usable Gates 1,250 1,250
Macrocells 64 —
Logic Array Blocks (LABs) 4 —
User I/O 66 —
Supply Voltage (Core / I/O) 3.3 V —
Pin-to-Pin Delay (tPD) 10 ns (-10 speed grade) 4.5 ns
Maximum Internal Frequency 227.3 MHz (counter) —
Packhaging 100-pin TQFP (industrial) 100-pin TQFP
Temperature na Operasyon -40 C to +85 C (industrial) 0C to +70C (commercial)
JTAG (IEEE 1149.1) Yes —
PCI Compliance PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) —
MultiVolt I/O Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing —
Lead-Free Status Contains Lead —
Tindminan RoHS RoHS Non-Compliant [DATA_NEEDED: RoHS status]
Macro Cells — 64
Logic Array Blocks — 2
User I/O Pins — 66
Counter Frequency — 222.2 MHz (max)
Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
Uri ng Pagpapasok — Surface Mount
Programming Interface — IEEE Std. 1149.1 JTAG (ISP)
ISP Standard — IEEE Std. 1532
Process Technology — CMOS EEPROM

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