EPM3064ATI44-4N vs EPM3064ATC44-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI44-4N sa pamamagitan ng Altera at EPM3064ATC44-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATI44-4N EPM3064ATC44-7N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Logic Elements / Macrocells 64 macrocells —
Usable Gates 1,250 gates 1,250
Number of Logic Array Blocks (LABs) 4 LABs (16 macrocells each) —
Maximum Operating Frequency 222.2 MHz —
Pin-to-Pin Propagation Delay (tPD) 4.5 ns (-4 speed grade) —
Supply Voltage - Core (VCCINT) 3.3 V —
Supply Voltage - I/O (VCCIO) 3.3 V or 2.5 V —
User I/O Pins 34 I/O 34
Packhaging 44-pin TQFP 44-pin TQFP
Temperature na Operasyon -40C to +85C (industrial) 0°C to +85°C (commercial)
Programming Interface IEEE Std. 1149.1 JTAG, IEEE Std. 1532 ISP —
Configuration Memory EEPROM (non-volatile) —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: rohs status] Compliant
Macro Cells — 64
Logic Array Blocks — 2
Bilang ng Pins — 44
Speed Grade — -7 (7.5 ns pin-to-pin delay)
Pin-to-Pin Delay (tPD) — 7.5 ns
Maximum Counter Frequency — 192.3 MHz (-7 grade)
Supply Voltage (VCC) — 3.3 V
MultiVolt I/O — 1.8 V / 2.5 V / 3.3 V
Programmability — EEPROM, in-system programmable (ISP)
JTAG Interface — IEEE Std. 1149.1 compliant
ISP Standard — IEEE Std. 1532 compliant
Boundary-Scan Test (BST) — Built-in, JTAG-driven

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