EPM3128ATC100-5 vs EPM3128ATI100-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATC100-5 sa pamamagitan ng Intel at EPM3128ATI100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3128ATI100-10 - 128-Macro MAX 3000A CPLD, 10ns TQFP-100 | Altera
EPM3128ATI100-10 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3128ATC100-5 | EPM3128ATI100-10 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Series | MAX 3000A | — |
| Family | CPLD - MAX 3000A | MAX 3000A |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 80 | 80 |
| Dedicated Inputs | 4 | — |
| Pin-to-Pin Delay (tpd) | 5 ns (commercial); 7.5 ns | — |
| Maximum Frequency (fCNT) | 192.3 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 3.3 V | — |
| Output Drive Voltage | 2.5 V or 3.3 V (programmable) | — |
| Input Tolerance | 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | — |
| JTAG Boundary Scan | Yes, IEEE Std. 1149.1 | — |
| Temperature na Operasyon | 0 °C to 70 °C (Commercial) | -40 °C to +85 °C (industrial) |
| Packhaging | 100-pin TQFP (Fine Line) | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 128 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| MultiVolt I/O Levels | — | 5.0 V / 3.3 V / 2.5 V compatible |
| Programmability | — | EEPROM, 3.3 V in-system (JTAG) |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Boundary-Scan (JTAG) | — | IEEE 1149.1 compliant |