EPM3128ATC100-5 vs EPM3128ATI100-10 比較
詳細並排比較 EPM3128ATC100-5 由 Intel 與 EPM3128ATI100-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3128ATC100-5 | EPM3128ATI100-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Series | MAX 3000A | — |
| Family | CPLD - MAX 3000A | MAX 3000A |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 80 | 80 |
| Dedicated Inputs | 4 | — |
| Pin-to-Pin Delay (tpd) | 5 ns (commercial); 7.5 ns | — |
| Maximum Frequency (fCNT) | 192.3 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 3.3 V | — |
| Output Drive Voltage | 2.5 V or 3.3 V (programmable) | — |
| Input Tolerance | 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | — |
| JTAG Boundary Scan | Yes, IEEE Std. 1149.1 | — |
| 工作溫度 | 0 °C to 70 °C (Commercial) | -40 °C to +85 °C (industrial) |
| 封裝 | 100-pin TQFP (Fine Line) | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| 安裝類型 | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 128 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| MultiVolt I/O Levels | — | 5.0 V / 3.3 V / 2.5 V compatible |
| Programmability | — | EEPROM, 3.3 V in-system (JTAG) |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Boundary-Scan (JTAG) | — | IEEE 1149.1 compliant |