EPM3128ATC144-5N vs EPM3128ATI144-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATC144-5N sa pamamagitan ng Altera at EPM3128ATI144-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM3128ATC144-5N EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera

EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera

EPM3128ATC144-5N ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM3128ATC144-5N EPM3128ATI144-7N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Huling Pagbili
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Logic Family CMOS —
Macrocells 128 128
Usable Gates 2500 —
User I/O 96 —
Pin-to-Pin Logic Delay 5 ns —
Counter Frequency up to 227.3 MHz —
Supply Voltage (Core) 3.3 V —
I/O Logic Levels Supported 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
In-System Programmability Yes (3.3-V via JTAG) —
JTAG Boundary Scan IEEE Std 1149.1 compliant —
Packhaging 144-pin TQFP (20x20 mm) 144-pin TQFP
Temperature na Operasyon 0C to 70C (Commercial) -40C to +85C (industrial)
Tindminan RoHS Compliant (lead-free) —
Uri ng Pagpapasok Surface Mount —
Logic Capacity — 2.5K gates
Maximum Frequency (fMAX) — 129.9 MHz
Pin-to-Pin Propagation Delay — 7.5 ns (speed grade -7)
User I/O Pins — 96
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V / 2.5 V / 1.8 V
Programmable Logic Technology — CMOS EEPROM
Programming Interface — JTAG (IEEE Std 1149.1) in-system programmable
Terminal Pitch — 0.5 mm
JEDEC Package Code — S-PQFP-G144
MultiVolt I/O — Yes (interfaces with 5.0V/3.3V/2.5V/1.8V logic)

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