EPM3256AFC256-10 vs EPM3256AFC256-7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256AFC256-10 sa pamamagitan ng Altera at EPM3256AFC256-7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3256AFC256-10 EPM3256AFC256-7
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 3000A MAX 3000A
Logic Family CMOS (EEPROM-based) —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 256 256
Usable Gates 5,000 10,000
Logic Array Blocks (LABs) 16 (16 macrocells each) 16
Maximum User I/Os 161 —
Propagation Delay (tPD) 10 ns —
Internal Counter Frequency (fCNT) 95.2 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Voltage Tolerance 5.0 V tolerant —
In-System Programmability Yes (3.3 V ISP via JTAG IEEE 1149.1) IEEE Std. 1532-compliant 3.3-V ISP
Temperature na Operasyon 0°C to +70°C (Commercial) 0 °C to 70 °C (Commercial)
Packhaging 256-ball FBGA (Fine-Line BGA) FBGA-256 (FineLine BGA), 256 balls
Pitch [DATA_NEEDED: BGA ball pitch] —
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
User I/Os — 161
Pin-to-Pin Logic Delay — 4.5 ns (max)
Counter Frequency — 227.3 MHz (max)
Propagation Delay (tpd) — 10 ns
Core Voltage — 3.3 V
I/O Compatibility — 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O)
Process Technology — CMOS EEPROM, 0.30 µm
Boundary-Scan Test — JTAG (IEEE 1149.1)
Speed Grade — -7

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