EPM3512AFC256-19 vs EPM3512AFC256-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-19 sa pamamagitan ng Altera at EPM3512AFC256-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-19 EPM3512AFC256-20
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Usable Gates 10000 —
Logic Array Blocks (LABs) 16 —
Maximum Operating Frequency 80 MHz —
Pin-to-Pin Delay (tPD) 7.5 ns —
Speed Grade -19 -20 (20 ns tPD)
User I/O Pins 208 —
Packhaging 256-ball FineLine BGA (FC) 256-ball FBGA (Fine-pitch BGA)
Supply Voltage VCCINT 3.3 V —
I/O Supply Voltage VCCIO 2.5 V or 3.3 V (5.0 V tolerant inputs) —
Programming Interface JTAG (IEEE 1149.1) / ISP (IEEE 1532) —
Process Technology 0.30 µm CMOS EEPROM —
Temperature na Operasyon -40C to +85C (industrial) [DATA_NEEDED: operating temperature range]
Non-volatile Configuration Yes (EEPROM-based) —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Typical Usable Gates — 10,000
Bilang ng Pin — 256
Operating Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Voltage (VCCIO) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
I/O Standards — LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type — EEPROM (non-volatile)
In-System Programmability — Yes (JTAG IEEE 1149.1)
JTAG Support — Yes (boundary-scan + ISP)
Level ng MSL — [DATA_NEEDED: MSL moisture sensitivity level]
Configuration Memory — Internal EEPROM

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