EPM3512AFC256-2 vs EPM3512AFC256-18 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-2 sa pamamagitan ng Altera at EPM3512AFC256-18 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 ObsoletePagsanggunian na paghahambing
| Parametro | EPM3512AFC256-2 | EPM3512AFC256-18 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 212 | 212 |
| Propagation Delay (tPD, -2 grade) | [DATA_NEEDED: tPD ns] | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX MHz] | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Output Drive Voltage | 2.5 V or 3.3 V (MultiVolt) | — |
| Input Tolerance | 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Packhaging | BGA-256 (FineLine BGA) | 256-ball FineLine BGA (FCBGA) |
| Ball Pitch | 1.0 mm | 1.0 mm |
| Programming Interface | JTAG (IEEE Std 1149.1) / ByteBlaster | — |
| Process Technology | 0.30 um CMOS EEPROM | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: industrial/commercial grade] |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not specified in retrieved data] |
| Speed Grade | -2 | — |
| Pin-to-Pin Delay (tPD1) | — | 18 ns |
| Global Clock Networks | — | 4 |
| VCCINT (Core Supply) | — | 3.0 V to 3.6 V (3.3 V typical) |
| VCCIO (I/O Supply) | — | 2.5 V or 3.3 V (MultiVolt) |
| Programming Technology | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) |
| Uri ng Pagpapasok | — | Surface Mount |